product is completely pb-free si21102 vishay siliconix new product document number: 73213 s-50474?rev. b, 14-mar-05 www.vishay.com 1 150-ma ultra low-noise ldo regulator with error flag and discharge features ultra low dropout?130 mv at 150-ma load low noise?75 v (rms) (10-hz to 100-khz bandwidth) out ? of ? regulation error flag (power good) shutdown control 110- a ground current at 150-ma load 1.5% guaranteed output voltage accuracy 300-ma peak output current capability uses low esr ceramic capacitors fast start-up (50 s) fast line and load transient response ( 30 s) 1- a maximum shutdown current output current limit reverse battery protection built-in short circuit and thermal protection output, auto-discharge in shutdown mode fixed 1.2, 1.8, 2.0, 2.2, 2.5, 2.6, 2.7, 2.8, 2.85, 2.9, 3.0, 3.3, 3.5, 3.6, 5.0-v output voltage options sc70-5 package applications cellular phones, wireless handsets noise-sensitive electronic systems, laptop and palmtop computers pdas pagers digital cameras mp3 player wireless modem description the sip21102 is a 150-ma cmos ldo (low dropout) voltage regulator. it is the perfect choice for low voltage, low power applications. an ultra low ground current makes this part attractive for battery operated power systems. the sip21102 also offers ultra low dropout voltage to prolong battery life in portable electronics. systems requiring a quiet voltage source, will benefit from the sip21 102?s low output noise. the sip21102 is designed to maintain regulation while delivering 300-ma peak current, making it ideal for systems that have a high surge current upon turn-on. for better transient response and regulation, an active pull-down circuit is built into the sip21102 to clamp the output voltage when it rises beyond normal regulation. the sip21102 automatically discharges the output voltage by connecting the output to ground through a 100- n-channel mosfet when the device is put in shutdown mode. the sip21102 features reverse battery protection to limit reverse current flow to approximately 1- a in the event reversed battery is applied at the input, thus preventing damage to the ic. the sip21102 is available in a lead (pb)-free 5-pin sc70 package for operation over the industrial operating range ( ? 40 c to 85 c). typical application circuit 3 2 sip21102 1 4 5 v in gnd sd v out error v in sd v out 1 f 1 f 51 k error sc70, 5-lead
si21102 vishay siliconix new product www.vishay.com 2 document number: 73213 s-50474?rev. b, 14-mar-05 absolute maximum ratings absolute maximum ratings input voltage, v in to gnd ? 6.0 to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v sd (see detailed description) ? 0.3 v to v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current, i out short circuit protected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output v oltage, v out ? 0.3 v to v in + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package power dissipation, (p d ) b 384 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal resistance, ( ja ) a 207 c/w . . . . . . . . . . . . . . . . . . . . . . . . . maximum junction temperature, t j(max) 150 c . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. device mounted with all leads soldered or welded to pc board. b. derate 4.8 mw/ c above t a = 70 c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating range input v oltage, v in 2 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v sd 0 v to v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ambient temperature, t a ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . c in = c out = 1 f (ceramic), c bp = 0.01 f (ceramic) maximum esr of c out : 0.4 specifications test conditions unless specified t a = 25 c , v in = v out(nom) + 1 v , i out = 1 ma , limits ? 40 to 85 c parameter symbol t a = 25 c , v in = v out(nom) + 1 v , i out = 1 ma , c in = 1 f, c out = 1.0 f, v sd = 1.5 v temp a min b typ c max b unit start-up bp current i out on/off = high room 1 ma input voltage range v in full 2 6 v output voltage accuracy v out 1 ma i out 150 ma room ? 1.5 1 1.5 % output voltage accuracy v out 1 ma i out 150 ma full ? 2.5 1 2.5 % line regulation (v out 3 v) full ? 0.06 0.18 line regulation (3.0 v v out 3.6 v) v out 100 v in v out(nom) from v in = v out(nom) + 1 v to v out(nom) + 2 v full 0 0.3 %/v line regulation (5-v v ersion) in out(nom) from v in = 5.5 v to 6 v full 0 0.4 i out = 1 ma room 1 dt vlt dg i out = 50 ma room 45 80 dropout voltage d, g (v out(nom) 2.6 v) i out = 50 ma full 50 90 (v out(nom) 2 . 6 v) i out = 150 ma room 130 180 v in ? v out i out = 150 ma full 220 mv v in v out i out = 50 ma room 65 100 mv dro p out volta g e d, g i out = 50 ma full 120 dropout voltage d, g (v out(nom) 2.6 v, v in 2 v) i out = 150 ma room 190 250 () i out = 150 ma full 300 i out = 0 ma room 100 150 ground pin current e, g i out = 0 ma full 180 ground pin current e, g (v out(nom) 3 v) i out = 150 ma room 110 200 () i gnd i out = 150 ma full 230 a i gnd i out = 0 ma room 110 170 a ground pin current e i out = 0 ma full 200 ground pin current e (v out(nom) 3 v) i out = 150 ma room 120 200 () i out = 150 ma full 230 peak output current i o(peak) v out 0.95 x v out(nom) . t pw = 2 ms full 300 ma f = 1 khz room 60 ripple rejection v out / v in i out = 150 ma f = 10 khz room 40 db ripple rejection v out / v in i out 150 ma f = 100 khz room 30 db
si21102 vishay siliconix new product document number: 73213 s-50474?rev. b, 14-mar-05 www.vishay.com 3 specifications limits ? 40 to 85 c temp a test conditions unless specified t a = 25 c, v in = v out(nom) + 1 v, i out = 1 ma, c in = 1 f, c out = 1.0 f, v sd = 1.5 v parameter unit max b typ c min b temp a test conditions unless specified t a = 25 c, v in = v out(nom) + 1 v, i out = 1 ma, c in = 1 f, c out = 1.0 f, v sd = 1.5 v symbol dynamic line regulation v o(line) v in : v out(nom) + 1 v to v out(nom) + 2 v t r /t f = 2 s, i out = 150 ma room 20 mv dynamic load regulation v o(load) i out : 1 ma to 150 ma, t r /t f = 2 s room 20 mv thermal shutdown junction temperature t j(s/d) room 150 c thermal hysteresis t hyst room 20 c reverse current i r v in = ? 6.0 v room 1 a short circuit current i sc v out = 0 v room 700 ma shutdown shutdown supply current i cc(off) v sd = 0 v room 0.1 1 a sd pin input voltage v sd high = regulator on (rising) full 1.5 v in v sd pin input voltage v sd low = regulator off (falling) full 0.4 v auto discharge resistance r_dis sip21102only room 100 sd pin input current f i in(sd ) v sd = 1.5 v, v in = 6 v room 0.7 a sd hysteresis v hyst(sd ) full 150 mv v out turn-on time t on v sd (see figure 1), i load = 100 na 50 s error output error high leakage i off error v in . v out in regulation full 1 a error low voltage v ol i sink = 0.5 ma full 0.4 v error volta g e threshold v err o r v out below v out(nom) g , v in 2 v v out falling, i out = 1 ma, v out(nom) 2 v full ? 2 ? 4 ? 6 error voltage threshold v error v out(nom) g 2 v, v in 2 v full ? 4 % error voltage threshold hysteresis v hyst(error ) room 1.5 % notes a. room = 25 c, full = ? 40 to 85 c. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. typical values are for design aid only, not guaranteed nor subject to production testing. typical values for dropout voltage at v out 2 v are measured at v out = 3.3 v, while typical values for dropout voltage at v out < 2 v are measured at v out = 1.8 v. d. dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-v differential, provided that v in does not not drop below 2.0 v. e. ground current is specified for normal operation as well as ?drop-out? operation. f. the device?s shutdown pin includes a typical 2-m internal pull-down resistor connected to ground. g. v out(nom) is v out when measured with a 1-v differential to v in. timing waveforms figure 1. timing diagram for power-up v sd 0.95 v nom v out v nom t on 0 v v in t r 1 s
si21102 vishay siliconix new product www.vishay.com 4 document number: 73213 s-50474?rev. b, 14-mar-05 pin configuration sd 3 2 sc70, 5-lead 1 4 5 v in gnd v out error pin description pin number name function 1 v in input supply pin. bypass this pin with a 1- f ceramic or tantalum capacitor to ground 2 gnd ground pin. for better thermal capability, directly connected to large ground plane 3 sd by applying less than 0.4 v to this pin, the device will be turned off. connect this pin to v in if unused 4 error the open drain output is an error flag output which goes low when v out drops 4% below its nominal voltage. 5 v out output voltage. connect c out between this pin and ground. ordering information part number marking voltage temp. range pkg. sip21102dr-12-e3 y0ll 1.2 sip21102dr-18-e3 e0ll 1.8 sip21102dr-20-e3 e1ll 2.0 sip21102dr-22-e3 e2ll 2.2 sip21102dr-25-e3 e3ll 2.5 sip21102dr-26-e3 e4ll 2.6 sip21102dr-27-e3 e5ll 2.7 sip21102dr-28-e3 e6ll 2.8 ? 40 to 85 c sc70-5 sip21102dr-285-e3 e7ll 2.85 sip21102dr-29-e3 e8ll 2.9 sip21102dr-30-e3 e9ll 3.0 sip21102dr-33-e3 f0ll 3.3 sip21102dr-35-e3 f1ll 3.5 SIP21102DR-36-E3 f2ll 3.6 sip21102dr-50-e3 f3ll 5.0 note: ll = lot code
si21102 vishay siliconix new product document number: 73213 s-50474?rev. b, 14-mar-05 www.vishay.com 5 typical characteristics (internally regulated, 25 c unless noted) ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 ? 0.0 0.2 0.4 ? 40 ? 15 10 35 60 85 normalized v out vs. t emperature ambient temperature ( c) (%) v out 0 50 100 150 200 250 300 234567 no load gnd pin current vs. input voltage ( i gnd a) input voltage (v) i out = 0 ma i out = 150 ma i out = 75 ma ? 40 c 85 c 50 75 100 125 150 0 25 50 75 100 125 150 gnd current vs. load current ( i gnd a) load current (ma) 600 625 650 675 700 725 750 ? 40 ? 15 10 35 60 85 output short circuit current vs. t emperature 25 c (ma) i sc ambienttemperature ( c) 25 c ? 80 ? 60 ? 40 ? 20 0 10 100 1000 10000 100000 1000000 power supply rejection frequency (hz) gain (db) c in = 1 f c out = 1 f i load = 150 ma v out = 3.0 v ? 0.75 ? 0.60 ? 0.45 ? 0.30 ? 0.15 0.00 0.15 0.30 0 25 50 75 100 125 150 normalized output voltage vs. load current output voltage (%) load current (ma) v out = 2.6 v v in = v out(nom) + 1 v v out = 3.0 v v in = 4.0 v v in = v out(nom) + 1 v ? 40 c 85 c
si21102 vishay siliconix new product www.vishay.com 6 document number: 73213 s-50474?rev. b, 14-mar-05 typical characteristics (internally regulated, 25 c unless noted) 0 50 100 150 200 250 300 350 0 60 120 180 240 300 dropout v oltage vs. load current i load (ma) (mv) v drop 0 50 100 150 200 250 300 350 ? 50 ? 25 0 25 50 75 100 125 150 dropout v oltage vs. t emperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0123456 v in ? v out transfer characteristic v in (v) (v) v out junction temperature ( c) 0 50 100 150 200 250 300 350 400 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 dropout voltage vs. v out dropout voltage (mv) v out (mv) v drop i out = 0 ma i out = 150 ma i out = 10 ma i out = 75 ma v out = 3.0 v v out = 3.0 v v out = 3.0 v i out = 10 ma i out = 75 ma i out = 150 ma i out = 300 ma i out = 300 ma
si21102 vishay siliconix new product document number: 73213 s-50474?rev. b, 14-mar-05 www.vishay.com 7 typical waveforms load t ransient response-1 i load 100 ma/div v out 10 mv/div v out = 3.0 v c out = 1 f i load = 1 to 150 ma t rise = 2 sec load t ransient response-2 v out = 3.0 v c out = 1 f i load = 150 to 1 ma t fall = 2 sec 20 s/div i load 100 ma/div v out 10 mv/div linetransient response-1 v out 10 mv/div v in 2 v/div v instep = 4 to 5 v v out = 3 v c out = 1 f c in = 1 f i load = 150 ma t rise = 5 sec 20 s/div linetransient respons-2 v instep = 5 to 4 v v out = 3 v c out = 1 f c in = 1 f i load = 150 ma t fall = 5 sec 20 s/div 20 s/div v out 10 mv/div v in 2 v/div
si21102 vishay siliconix new product www.vishay.com 8 document number: 73213 s-50474?rev. b, 14-mar-05 typical waveforms output noise v out 2 00 v/div noise spectrum 4 ms/div 10 hz v in = 4 v v out = 3 v i out = 150 ma bw = 10 hz to 100 khz 10 0.01 1 mhz v in = 4 v v out = 3 v i load = 150 ma v hz output spectral noise density block diagram sip21102 v in reference ? + thermal sensor shutdown control gnd error v out reverse polarity protection current limit sd
si21102 vishay siliconix new product document number: 73213 s-50474?rev. b, 14-mar-05 www.vishay.com 9 detailed description the sip21102 is a low-noise, low drop-out and low quiescent current linear voltage regulator, packaged in a small footprint sc70-5 package. the sip21102 can supply loads up to 300 ma. as shown in the block diagram, the circuit consists of a bandgap reference error, amplifier, p-channel pass transistor and feedback resistor string. an external bypass capacitor connected to the bp pin reduces noise at the output. additional blocks, not shown in the block diagram, include a precise current limiter, reverse battery and current protection and thermal sensor. thermal overload protection the thermal overload protection limits the total power dissipation and protects the device from being damaged. when the junction temperature exceeds 150 , the device turns the p-channel pass transistor off. reverse battery protection the sip21102 has a battery reverse protection circuitry that disconnects the internal circuitry when v in drops below the gnd voltage. there is no current drawn in such an event. when the sd pin is hardwired to v in , the user must connect the sd pin to v in via a 100-k resistor if reverse battery protection is d esired. hardwiring the sd pin directly to the v in pin is allowed when reverse battery protection is not desired. error error is an open drain output that goes low when v out is less than 4% of its normal value. to obtain a logic level output, connect a pull-up resister from error to v out or any other voltage equal to or less than v in . error pin is high impedance (off) when sd pin is low. auto-discharge v out has an internal 100- (typ.) discharge path to ground when the sd pin is low. stability the circuit is stable with only a small output capacitor equal to 6 nf/ma (= 1 f @ 150 ma). since the bandwidth of the error amplifier is around 1 ? 3 mhz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150-ma load current, an esr <0.4 is necessary. parasitic inductance of about 10 nh can be tolerated. vishay siliconix maintains worldwide manufacturing c apability. pr oducts may be manufactured at on e of several qualified locati ons. reliability data for silicon technology and package reliability repr esent a composite of all qualified locations. for re lated documents such as package/tape drawings, par t marking, and reliability data, see http://www.vishay.com/ppg?73213 .
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